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| 12-bit, 200 msps/500 msps txdac+ ? with 2/4/8 interpolation and signal processing preliminary technical data AD9782 rev. prc information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features 12-bit resolution, 200 msps input data rate selectable 2/4/8 interpolation filters selectable f dac /2, f dac /4, f dac /8 modulation modes single or dual-channel signal processing selectable image rejection hilbert transform flexible calibration engine direct if transmission features serial control interface versatile clock and data interface sfdr 90 dbc @10 mhz wcdma aclr = 80 dbc @ 40 mhz if dnl = 0.75 lsb inl = 1.5 lsb 3.3 v compatible digital interface on-chip 1.2 v reference 80-lead thermally enhanced tqfp package applications digital quadrature modulation architectures multicarrier wcdma, gsm, tdma, dcs, pcs, cdma systems product description the AD9782 is a 12-bit, high speed, cmos dac with 2/4/8 interpolation and signal processing features tuned for communications applications. it offers state of the art distortion and noise performance. the AD9782 was developed to meet the demanding performance requirements of multicarrier and third generation base stations. the selectable interpolation filters simplify interfacing to a variety of input data rates while also taking advantage of oversampling performance gains. the modulation modes allow convenient bandwidth placement and selectable sideband suppression. the flexible clock interface accepts a variety of input types such as 1 v p-p sine wave, cmos, and lvpecl in single ended or differential mode. internal dividers generate the required data rate interface clocks. the AD9782 provides a differential current output, supporting single-ended or differential applications; it provides a nominal full-scale current from 10 ma to 20 ma. the AD9782 is manufactured on an advanced low cost 0.25 m cmos process. functional block diagram 16-bit dac reference circuits calibration spi zero stuff hilbert ? t 0 90 0 90 0 90 re()/im() 2 2 2 latch clock multiplier 2 2 2 latch q i data assembler data port synchronizer f dac /2 f dac /4 f dac /8 1 2 4 8 clock distribution and control 2/4/8/16 1/2/4/8/16 clk+ clk? lpf dataclk/ pll_lock p2b[15:0] p1b[15:0] fsadj refio i outa i outb sdio sdo csb sclk reset 03152-prd-001 figure 1.
AD9782 preliminary technical data rev. prc | page 2 of 52 table of contents product highlights ........................................................................... 3 AD9782?specifications.................................................................... 4 dc specifications ......................................................................... 4 dynamic specifications ............................................................... 5 digital specifications ................................................................... 6 pin configuration and function descriptions............................. 7 clock .............................................................................................. 7 analog............................................................................................ 8 data ................................................................................................ 8 serial interface .............................................................................. 9 definitions of specifications ......................................................... 10 typical performance charatceristics ........................................... 12 serial control interface.................................................................. 17 general operation of the serial interface ............................... 17 instruction byte .......................................................................... 17 serial interface port pin descriptions ..................................... 17 msb/lsb transfers..................................................................... 18 notes on serial port operation ................................................ 18 mode control (via spi port) ......................................................... 19 digital filter specifications ........................................................... 23 digital interpolation filter coefficients.................................. 23 AD9782 clock/data timing..................................................... 24 interpolation modes .................................................................. 27 real and complex signals......................................................... 28 modulation modes..................................................................... 29 power dissipation ...................................................................... 34 dual channel complex modulation with hilbert ................ 35 hilbert transform implementation......................................... 36 operating the AD9782 rev e evaluation board........................ 40 power supplies............................................................................ 40 pecl clock driver .................................................................... 40 data inputs.................................................................................. 41 spi port ........................................................................................ 41 operating with pll disabled ................................................... 41 operating with pll enabled .................................................... 42 analog output ............................................................................ 42 outline dimensions ....................................................................... 52 esd caution................................................................................ 52 revision history revision prc: preliminary version preliminary technical data AD9782 rev. prc | page 3 of 52 product highlights 1. the AD9782 is a member of a high speed interpolating txdac+ family with 16-/14-/12-bit resolutions. 2. 2/4/8 user selectable interpolating filter eases data rate and output signal reconstruction filter requirements. 3. 200 msps input data rate. 4. ultrahigh speed 500 msps dac conversion rate. 5. internal pll/clock divider provides data rate clock for easy interfacing. 6. flexible clock with single-ended or differential input: cmos, 1 v p-p sine wave and lvpecl capability. 7. complete cmos dac function operates from a 2.7 v to 3.6 v single analog (avdd) supply and a 2.5 v (dvdd) digital supply. the dac full-scale current can be reduced for lower power operation, and a sleep mode is provided for low-power idle periods. 8. on-chip voltage reference: the AD9782 includes a 1.20 v temperature-compensated band gap voltage reference. AD9782 preliminary technical data rev. prc | page 4 of 52 AD9782?specifications dc specifications table 1. t min to t max , avdd1, avdd2 = 3.3 v, acvdd, advdd, clkvdd, dvdd, drvdd = 2.5 v, i outfs = 20 ma, unless otherwise noted parameter min typ max unit resolution 12 bits dc accuracy 1 integral nonlinearity 1.5 lsb differential nonlinearity 0.75 lsb analog output offset error of fsr gain error (ithout internal reference) of fsr gain error (ith internal reference) of fsr full-scale output current 2 10 20 ma output compliance range 1.0 1.0 v output resistance tbd k? output capacitance 3 pf reference output reference voltage 1.14 1.20 1.26 v reference output current 3 1 a reference input input compliance range 0.1 1.25 v reference input resistance (ext reference mode) 10 m? small signal bandwith 0.5 mhz temperature coefficients unipolar offset drift ppm of fsr/c gain drift (ithout internal re ference) ppm of fsr/c gain drift (ith internal refe rence) ppm of fsr/c reference voltage drift ppm /c poer suppl avdd1, avdd2 voltage range 3.1 3.3 3.5 v analog supply current (i avdd1 ) ma analog supply current (i avdd2 ) ma i avdd1 in sleep mode ma acvdd, advdd voltage range 2.35 2.5 2.65 v analog supply current (i acvdd ) ma analog supply current (i advdd ) ma clkvdd voltage range 2.35 2.5 2.65 v clock supply current (i clkvdd ) ma dvdd voltage range 2.35 2.5 2.65 v digital supply current (i dvdd ) ma drvdd voltage range 2.35 2.5/3.3 3.5 v digital supply current (i drvdd ) ma nominal power dissipation 4 1.25 operating range 40 85 c 1 measured at iouta driing a irtual ground. 2 nominal full-scale current, i outfs , is 32 the i ref current. 3 use an external amplifier to drie any external load. 4 measured under the fo llowing conditions f data = 125 msps, f dac = 500 msps, 4 interpolation, f dac /4 modulation, hilbert off. preliminary technical data AD9782 rev. prc | page 5 of 52 dynamic specifications table 2. t min to t max , avdd1, avdd2 = 3.3 v, acvdd, advdd, clkvdd, dvdd, drvdd = 2.5 v, i outfs = 20 ma, differential transformer coupled output, 50 ? doubly terminated, unless otherwise noted parameter min typ max unit dnamic performance maximum dac output update rate (f dac ) 500 msps output settling time (t st ) (to 0.025) ns output propogation delay 5 (t pd ) ns output rise time (1090) 6 ns output fall time (9010) 6 ns output noise (i outfs = 20 ma) pahz ac linearitbaseband mode spurious-free dynamic rang e (sfdr) to nyuist (f out = 0 dbfs) f data = 160 msps f out = 1 mhz 95 dbc f data = msps f out = mhz dbc f data = msps f out = mhz dbc f data = msps f out = mhz dbc f data = msps f out = mhz dbc f data = msps f out = mhz two-tone intermodulatio n (imd) to nyuist (f out1 = f out2 = 6 dbfs) f data = 160 msps f out1 =25 mhz f out2 = 31 mhz 80 dbc f data = msps f out1 = mhz f out2 = mhz dbc f data = msps f out1 = mhz f out2 = mhz dbc f data = msps f out1 = mhz f out2 = mhz dbc f data = msps f out1 = mhz f out2 = mhz dbc f data = msps f out1 = mhz f out2 = mhz dbc total harmonic distortion (thd) f data = msps f out = mhz 0 dbfs db f data = msps f out = mhz 0 dbfs db signal-to-noise ratio (snr) f data = msps f out = mhz 0 dbfs dbfs f data = msps f out = mhz 0 dbfs dbfs adjacent channel power ratio (acpr) cdma with mhz b, mhz channel spacing if = 16 mhz, f data = 65.536 msps dbc if = 32 mhz, f data = 131.072 msps dbc four-tone intermodulation mhz, mhz, mhz and mhz at 12 dbfs (f data = msps, missing center) dbfs ac linearitif mode four-tone intermodulation at if = mhz mhz, mhz, mhz and mhz at dbfs dbfs f data = msps, f dac = mhz 5 propagation delay is delay from clk input to dac update. 6 measured single-ended into 50 ? load. AD9782 preliminary technical data rev. prc | page 6 of 52 digital specifications table 3. t min to t max , avdd1, avdd2 = 3.3 v, acvdd, advdd, clkvdd, dvdd = 2.5 v, i outfs = 20 ma, unless otherwise noted parameter min typ max unit digital inputs logic 1 voltage drvdd 0.9 drvdd v logic 0 voltage 0 0.9 v logic 1 current 10 10 a logic 0 current 10 10 a input capacitance 5 pf lock inputs input voltage range 0 2.65 v common-mode voltage 0.75 1.5 2.25 v differential voltage 0.5 1.5 v pll clock enabled input setup time (t s ) ns input hold time (t h ) ns latch pulse idth (t lp ) ns pll clock disabled input setup time (t s ) ns input hold time (t h ) ns latch pulse idth (t lp ) ns clk to plllock delay (t od ) ns preliminary technical data AD9782 rev. prc | page 7 of 52 pin configuration and fu nction descriptions 80 79 78 77 76 71 70 69 68 67 66 65 75 74 73 72 64 63 62 61 16 1 2 3 4 5 6 7 8 9 10 11 13 14 15 12 17 18 20 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pin 1 identifier 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 nc = no connect nc advdd adgnd acvdd acgnd avdd2 agnd2 avdd1 agnd1 iouta ioutb agnd1 avdd1 agnd2 avdd2 acgnd acvdd adgnd advdd dnc clkvdd lpf clkvdd clkgnd clk+ clk? clkgnd dgnd dvdd p1b15 p1b14 p1b13 p1b12 p1b11 p1b10 dgnd dvdd p1b9 p1b8 p1b7 fsadj refio reset csb sclk sdio sdo dgnd dvdd p2b0 p2b1 p2b2 p2b3 p2b4 p2b5 dgnd p1b6 p1b5 p1b4 p1b3 dgnd dvdd p1b2 p1b1 p1b0 drvdd iqsel/p2b15 oneportclock/p2b14 p2b13 dgnd dvdd dataclk/pll_lock AD9782 top view (not to scale) dvdd p2b6 p2b7 p2b8 p2b12 p2b11 p2b10 p2b9 03150-prd-001 figure 2. pin configuration clock table 4. clock pin function descriptions pin no. mnemonic direction description 5, 6 clk, clk i differential clock input. 2 lpf i/o pll loop filter. plockext 04h0 dclkext 02h3 mode 0 0 pin configured for input of channel data rate or synchronizer clock. internal clock synchronizer may be turned on or off with dclkcrc (02h2). 0 1 pin configured for output of channe l data rate or synchronizer clock 31 dataclk/plllock i/o 1 x internal clock pll status output 0 internal clock pll is not locked. 1 internal clock pll is locked. 1, 3 clkvdd clock domain 2.5 v. 4, 7 clkgnd clock domain 0 v. AD9782 preliminary technical data rev. prc | page 8 of 52 analog table 5. analog pin function descriptions pin no. mnemonic direction description 59 refio a reference. 60 fsad a full-scale adjust. 70, 71 ioutb, iouta a differential dac output currents. 61 dnc do not connect. 62, 79 advdd analog domain digital content 2.5 v. 63, 78 adgnd analog domain digital content 0 v. 64, 77 acvdd analog domain clock content 2.5 v. 65, 76 acgnd analog domain clock content 0 v. 66, 75 avdd2 analog domain clock switching 3.3 v. 67, 74 agnd2 analog domain switching 0 v. 68, 73 avdd1 analog domain uiet 3.3 v. 69, 72 agnd1 analog domain uiet 0 v. data table 6. data pin function descriptions pin no. mnemonic direction description input data port one. oneport 02h6 mode 0 latched data routed for 1 channel processing. 1015, 1824, 2729 p1b15p1b0 i 1 latched data demultiplexed by i sel and routed for interleaed i/ processing. oneport 02h6 ipol 02h1 isel/ p2b15 mode (ipol == 0) 0 x x latched data routed to channel bit 15(msb) processing. 1 0 0 latched data on data port one routed to channel processing. 1 0 1 latched data on data port one routed to i channel processing. 1 1 0 latched data on data port one routed to i channel processing. 32 isel/p2b15 i 1 1 1 latched data on data port one routed to channel processing. oneport 02h6 0 latched data routed for channel bit 14 processing. 33 oneportclk/p2b14 i/o 1 pin configured for output of cloc k at twice the channel data route. 34, 3743, 4651 p2b13p2b0 i input data port two bits 130. 30 drvdd digital output pin supply, 2.5 v or 3.3 v. 9, 17, 26, 36, 44, 52 dvdd digital domain 2.5 v. 8, 16, 25, 35, 45, 53 dgnd digital domain 0 v. preliminary technical data AD9782 rev. prc | page 9 of 52 serial interface table 7. serial interface pin function descriptions pin no. mnemonic direction description csb sdiodir 00h7 mode 1 x high impedance. 0 0 serial data output. 54 sdo o 0 1 high impedance. csb sdiodir 00h7 mode 1 x high impedance. 0 0 serial data output. 55 sdio i/o 0 1 serial data input/output depending on bit 7 of the serial instruction byte. 56 sclk i serial interface clock. 57 csb i serial interface chip select. 58 reset i resets entire chip to default state. AD9782 preliminary technical data rev. prc | page 10 of 52 definitions of specifications linearity error (integral nonlinearity or inl) linearity error is defined as the maximum deiation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (or dnl) dnl is the measure of the ariation in analog alue, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a d/a conerter is monotonic if the output either increases or remains constant as the digital input increases. offset error the deiation of the output current from the ideal of zero is called offset error. for i outa , 0 ma output is expected when the inputs are all 0s. for i outb , 0 ma output is expected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s, minus the output when all inputs are set to 0s. output compliance range the range of allowable oltage at the output of a current-output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (25c) alue to the alue at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per degree c. for reference drift, the drift is reported in ppm per degree c. power supply rejection the maximum change in the full-scale output as the supplies are aried from minimum to maximum specified oltages. settling time the time reuired for the output to reach and remain within a specified error band about its final alue, measured from the start of the output transition. glitch impulse asymmetrical switching times in a dac gie rise to undesired output transients that are uantified by a glitch impulse. it is specified as the net area of the glitch in pv-s. spurious-free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal oer the specified bandwidth. total harmonic distortion thd is the ratio of the rms sum of the first six harmonic components to the rms alue of the measured fundamental. it is expressed as a percentage or in decibels (db). signal-to-noise ratio (snr) s/n is the ratio of the rms alue of the measured output signal to the rms sum of all other spectral components below the nyuist freuency, excluding the first six harmonics and dc. the alue for snr is expressed in decibels. interpolation filter if the digital inputs to the dac are sampled at a multiple rate of f data (interpolation rate), a digital filter can be constructed which has a sharp transition band near f data /2. images which would typically appear around f dac (output data rate) can be greatly suppressed. pass-band freuency band in which any input applied therein passes unattenuated to the dac output. stop-band rejection the amount of attenuation of a freuency outside the pass- band applied to the dac, relatie to a full-scale signal applied at the dac input within the pass-band. group delay number of input clocks between an impulse applied at the deice input and peak dac output current. a half-band fir filter has constant group delay oer its entire freuency range impulse response response of the deice to an impulse applied to the input. preliminary technical data AD9782 rev. prc | page 11 of 52 adjacent channel power ratio (or acpr) a ratio in dbc between the measured power within a channel relatie to its adjacent channel. complex modulation the process of passing the real and imaginary components of a signal through a complex modulator (transfer function = e jwt = coswt jsinwt) and realizing real and imaginary components on the modulator output. complex image rejection in a traditional two part upconersion, two images are created around the second if freuency. these images are redundant and hae the effect of wasting transmitter power and system bandwidth. by placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower freuency image near the second if can be rejected. AD9782 preliminary technical data rev. prc | page 12 of 52 typical performance charatceristics (t min to t max , avdd1, avdd2 = 3.3 v, acvdd, advdd, clkvdd, dvdd, drvdd = 2.5 v, i outfs = 20 ma, differential transformer coupled output, 50 doubly terminated, unless otherwise noted) tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 3 single-tone spectrum@ f data = 65 msps with f out = f data /3 tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 4. in-band sfdr vs. f out @ f data = 65 msps tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 5. out-of-band sfdr vs. f out @ f data = 65 msps tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 6. single-tone spectrum @ f data = 78 msps with f out = f data /3 tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 7. in-band sfdr vs. f out @ f data = 78 msps tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 8. out-of-band sfdr vs. f out @ f data = 78 msps preliminary technical data AD9782 rev. prc | page 13 of 52 tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 9. single-tone spectrum @ f data = 160 msps with f out = f data /3 tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 10. in-band sfdr vs. f out @ f data = 160 msps tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 11. out-of-band sfdr vs. f out @ f data = 160 msps tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 12. third order imd products vs. f out @ f data = 65 msps tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 13. third order imd products vs. f out @ f data = 78 msps tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 14. third order imd products vs. f out @ f data = 160 msps AD9782 preliminary technical data rev. prc | page 14 of 52 tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 15. tpc 13. third order imd products vs. f out and interpolation rate 1 ? f data = 160 msps 2 ? f data = 160 msps 4 ? f data = 80 msps 8 ? f data = 50 msps tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 16. third order imd products vs. aout and interpolation rate f data = 50 msps for all cases 1 ? f dac = 50 msps 2 ? f dac = 100 msps 4 ? f dac = 200 msps 8 ? f dac = 400 msps tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 17. sfdr vs. avdd @ f out = 10 mhz; f dac = 320 msps f data = 160 msps tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 18. 3 rd order imd products vs. avdd @ f out = 10 mhz, f dac = 320 msps, f data = 160 msps tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 19. snr vs. data rate for f out = 5 mhz tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 20. sfdr vs. temperature @ f out = f data /11 preliminary technical data AD9782 rev. prc | page 15 of 52 tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 21. single tone spurious performance, f out = 10 mhz, f data = 150 msps, no interpolation tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 22. two tone imd performance, f data = 150 msps, no interpolation tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 23. single tone spurious performance, f out = 10 mhz, f data = 150 msps, interpolation = 2 tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 24. two tone imd performance, f data = 90 msps, interpolation = 4 tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 25. single tone spurious performance, f out = 10 mhz, f data = 80 msps, interpolation = 4 tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 26. two tone imd performance, f out = 10 mhz, f data = 50 msps, interpolation = 8 AD9782 preliminary technical data rev. prc | page 16 of 52 tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 27. single tone spurious performance, f out = 10 mhz, f data = 50 msps, interpolation = 8 tbd ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 all caps (initial caps) all caps (initial caps) figure 28. eight tone imd performance, f data = 160 msps, interpolation = 8 preliminary technical data AD9782 rev. prc | page 17 of 52 serial control interface AD9782 spi port interface sdo (pin 54) sdio (pin 55) s clk (pin 56) csb (pin 57) 03150-prd-002 figure 29. AD9782 spi port interface the AD9782 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry- standard microcontrollers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including both the motorola spi? and intel? ssr protocols. the interface allows read/write access to all registers that configure the AD9782. single or multiple byte transfers are supported as well as msb first or lsb first transfer formats. the AD9782?s serial interface port can be configured as a single pin i/o (sdio) or two unidirectional pins for in/out (sdio/sdo). general operation of the serial interface there are two phases to a communication cycle with the AD9782. phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9782, coincident with the first eight sclk rising edges. the instruction byte provides the AD9782 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the AD9782. a logic high on the cs pin, followed by a logic low, will reset the spi port timing to the initial state of the instruction cycle. this is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the spi port. if the spi port is in the midst of an instruction cycle or a data transfer cycle, none of the present data will be written. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the AD9782 and the system controller. phase 2 of the communication cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. normally, using one multibyte transfer is the preferred method. however, single byte data transfers are useful to reduce cpu overhead when register access requires one byte only. registers change immediately upon writing to the last bit of each transfer byte. instruction byte the instruction byte contains the following information: table 8. n1 n2 description 0 0 transfer 1 byte 0 1 transfer 2 bytes 1 0 transfer 3 bytes 1 1 transfer 4 bytes r/, bit 7 of the instruction byte, determines whether a read or a write data transfer will occur after the instruction byte write. logic high indicates read operation. logic 0 indicates a write operation. n1, n0, bits 6 and 5 of the instruction byte, determine the number of bytes to be transferred during the data transfer cycle. the bit decodes are shown in the following table table 9. msb lsb 17 16 15 14 13 12 11 10 r/ n1 n0 a4 a3 a2 a1 a0 a4, a3, a2, a1, a0 , bits 4, 3, 2, 1, 0 of the instruction byte, determine which register is accessed during the data transfer portion of the communications cycle. for multibyte transfers, this address is the starting byte address. the remaining register addresses are generated by the AD9782. serial interface port pin descriptions sclkserial clock . the serial clock pin is used to synchronize data to and from the AD9782 and to run the internal state machines. sclks maximum freuency is 15 mhz. all data input to the AD9782 is registered on the rising edge of sclk. all data is drien out of the AD9782 on the falling edge of sclk. csbchip select . actie low input starts and gates a communication cycle. it allows more than one deice to be used on the same serial communications lines. the sdo and sdio pins will go to a high impedance state when this input is high. chip select should stay low during the entire communication cycle. sdioserial data i/o . data is always written into the AD9782 on this pin. howeer, this pin can be used as a bidirectional data line. the configuration of this pin is controlled by bit 7 of register address 00h. the default is logic 0, which configures the sdio pin as unidirectional. sdoserial data out . data is read from this pin for protocols that use separate lines for transmitting and receiing data. in the case where the AD9782 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state. AD9782 preliminary technical data rev. prc | page 18 of 52 msb/lsb transfers the AD9782 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by register address datadir (00h[6]). the default is msb first. when this bit is set active high, the AD9782 serial port is in lsb first format. that is, if the AD9782 is in lsb first mode, the instruction byte must be written from least significant bit to most significant bit. multibyte data transfers in msb format can be completed by writing an instruction byte that includes the register address of the most significant byte. in msb first mode, the serial port internal byte address generator decrements for each byte required of the multibyte communication cycle. multibyte data transfers in lsb first format can be completed by writing an instruction byte that includes the register address of the least significant byte. in lsb first mode, the serial port internal byte address generator increments for each byte required of the multibyte communication cycle. the AD9782 serial port controller address will increment from 1fh to 00h for multibyte i/o operations if the msb first mode is active. the serial port controller address will decrement from 00h to 1fh for multibyte i/o operations if the lsb first mode is active. notes on serial port operation the AD9782 serial port configuration bits reside in bits 6 and 7 of register address 00h. it is important to note that the configuration changes immediately upon writing to the last bit of the register. for multibyte transfers, writing to this register may occur during the middle of communication cycle. care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. the same considerations apply to setting the software reset, swrst (00h[5]) bit. all other registers are set to their default values but the software reset doesn?t affect the bits in register address 00h and 04h. it is recommended to use only single byte transfers when changing serial port configurations or initiating a software reset. r/w n1 n0 a4a 3a 2a 1a 0 d7 d6 n d5 n d0 0 d1 0 d2 0 d3 0 d7 d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle data transfer cycle csb sclk sdio sdo 03152-prd-004 figure 30. serial register interface timing msb first a0 a1 a2 a3 a4 n0 n1 r/w d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n instruction cycle data transfer cycle csb sclk sdio sdo 03152-prd-005 figure 31. serial register interface timing lsb first instruction bit 6 instruction bit 7 csb sclk sdio t ds t ds t dh t pwh t pwl t sclk 03152-prd-006 figure 32. timing diagram for register write data bit n?1 data bit n csb sclk sdio sdo 03152-prd-007 t dv figure 33. timing diagram for register read preliminary technical data AD9782 rev. prc | page 19 of 52 mode control (via spi port) table 10. address bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 comms 00 sdiodir datadir srst sleep pdn plllock exref filter 01 interp1 interp0 stuff hpfx8 hpfx4 hpfx2 data 02 datafmt oneport dclkstr dclk pol dclkext dclkcrc ipol cradin modulate 03 channel hilbert moddual sideband mod1 mod0 pll 04 pllon pllmult1 pllmult0 plldiv1 plldiv0 plla1 plla0 plockext dclkcrc 05 datad3 datad2 datad1 data d0 modsnc modad2 modad1 modad0 06 resered 07 resered 08 resered 09 resered 0a resered 0b resered 0c resered version 0d version3 ve rsion3 version3 version3 calmemck 0e reserved reserved calmem1 ca lmen0 calckdiv2 ca lckdiv2 calckdiv2 memrdr 0f calstat calen xferstat xferen smemr smemrd fmemrd uncal memaddr 10 memaddr7 memaddr6 memaddr5 memaddr 4 memaddr3 memaddr2 memaddr1 memaddr0 memdata 11 memdata5 memdata4 memdat a3 memdata2 memdata1 memdata0 dcrstat 12 dcrstat 2 dcrstat1 dcrstat0 table 11. comms(00) bit direction default description sdiodir 7 i 0 0 sdio pin configured for input only during data transfer 1 sdio configured for input or output during data transfer datadir 6 i 0 0 serial da ta uses msb first format 1 serial data uses lsb first format srst 5 i 0 1 default all serial regist er bits, except addresses 00h and 04h sleep 4 i 0 1 dac output current off pdn 3 i 0 1 all analog and digital circ uitry, except serial interface, off pllock 1 o 0 0 ith pll on, indi cates that pll is not locked 1 ith pll on, indicates that pll is locked exref 0 i 0 0 internal band gap reference 1 external reference table 12. filter(01) bit direction default description interp10 76 i 00 00 no interpolation 01 interpolation 2 10 interpolation 4 11 interpolation 8 stuff 3 i 0 1 ero stuffing on hpfx8 2 i 0 0 8 interpolation filter configured for low pass 1 8 interpolation filter configured for high pass hpfx4 1 i 0 0 4 interpolation filter configured for low pass 1 4 interpolation filter configured for high pass hpfx2 0 i 0 0 2 interpolation filter configured for low pass 1 2 interpolation filter configured for high pass AD9782 preliminary technical data rev. prc | page 20 of 52 table 13. data(02) bit direction default description datafmt 7 i 0 0 twos co mplement data format 1 unsigned binary input data format oneport 6 i 0 0 i and input data onto ports one and two respectiely 1 i and input data interleaed onto port one dclkstr 5 i 0 0 dataclk pin 12 ma drie strength 1 dataclk pin 24 ma drie strength dclkpol 4 i 0 0 input data la tched on dataclk rising edge 1 input data latched on dataclk falling edge dclkext 3 i 0 0 ith plockext off, dataclk pin inputs channel data rate or modulator synchronizer clock 1 ith plockext off, dataclk pi n outputs channel data rate or modulator synchronizer clock dclkcrc 2 i 0 0 ith plockext off, and data clk pin as input, dataclk clock recoery off 1 ith plockext off, and dataclk pin as input, dataclk clock recoery on ipol 1 i 0 0 in one port mode, isel = 1 latches data into i channel, isel = 0 latches data into channel 1 in one port mode, isel = 0 latches data into i channel, isel = 1 latches data into channel gradin 0 i 0 0 gray decoder off 1 gray decoder on table 14. modulate(03) bit direction default description moddual 03h 5 channel 03h7 0 0 i channel processing routed to dac 0 1 channel processing routed to dac 1 0 modulator real output routed to dac channel 7 i 0 1 1 modulator imaginary output routed to dac hilbert 6 i 0 1 ith moddual on, hilbert transform on moddual 5 i 0 0 modulator uses a single channel 1 modulator uses both i and channels sideband 4 i 0 0 ith moddual on, lower sideband rejected 1 ith moddual on, upper sideband rejected mod10 32 i 00 00 no modulation 01 f s /2 modulation 10 f s /4 modulation 11 f s /8 modulation preliminary technical data AD9782 rev. prc | page 21 of 52 table 15. pll(04) bit direction default description pllon 7 i 0 0 pll off 1 pll on pllmulti10 65 i 00 pll multipl factor 00 2 00 4 00 8 00 16 plldiv10 43 i 00 pllmult rate diide factor 00/1 00/2 00/4 00/8 pllab10 21 i 00 pll autozero settling bandwidth as fraction of clk rate 00 /8 (lowest) 01 /4 10 /2 (highest) plockext 0 i 0 0 ith pll on, dataclk/plllock pin configured for dataclk input/output 1 ith pll on, dataclk/plllock pi n configured for output of plllock table 16. dclkcrc(05) bit direction default description datad30 74 i 0000 dataclk offset. twos complement respresentation 0111 7 0000 0 1000 -8 modsnc 3 i 00 0 ith plockext off, cha nnel data rate clock synchronizer mode 1 ith plockext off, state machine clock synchronizer mode f s /8 f s /4 f s /2 000 1 1 1 001 1/2 0 1 010 0 1 1 011 1/2 0 1 100 1 1 1 101 1/2 0 1 110 0 1 1 modad20 20 i 000 111 1/2 0 1 modulator coefficient offset table 17. version(0d) bit direction default description version30 30 o hardware ersion identifier AD9782 preliminary technical data rev. prc | page 22 of 52 table 18. calmemck(oe) bit direction default description calmem 54 o 00 calibration memory 00 uncalibrated 01 self calibration 10 factory calibration 11 user input calckdiv20 20 i 00 calibration clock diide ratio from channel data rate 000 /32 001 /64 110 /2048 111 /4096 table 19. memrdr(of) bit direction default description calstat 7 o 0 0 self calibration cycle not complete 1 self calibration cycle complete calen 6 i 0 1 self calibration in progress xferstat 5 o 0 0 factory memory transfer not complete 1 factory memory transfer complete xferen 4 i 0 1 factory memory transfer in progress smemr 3 i 0 1 rite static me mory data from external port smemrd 2 i 0 1 read static memory to external port fmemrd 1 i 0 1 read factory me mory data to external port uncal 0 i 0 1 use uncalibrated table 20. memaddr(10) bit direction default description memaddr 70 70 i/o 00000000 address of fact ory or static memory to be accessed table 21. memdata(11) bit direction default description memdata 50 50 i/o 000000 data or factory or static memory access table 22. dcrcstat(12) bit direction default description dcrcstat (2) 2 o 0 0 ith dataclk crc on, lock has neer been achieed 1 ith dataclk crc on, lock has been achieed at least once dcrcstat(1) 1 o 0 0 ith dataclk crc on, system is currently not locked 1 ith dataclk crc on, sy stem is currently locked dcrcstat(0) 0 o 0 0 ith dataclk cr c on, system is currently locked 1 ith dataclk crc on, system lost lock due to jitter preliminary technical data AD9782 rev. prc | page 23 of 52 digital filter specifications digital interpolation filter coefficients table 23. stage 1 interpolat ion filter coefficients lower coefficient upper coefficient integer value h(1) h(43) 9 h(2) h(42) 0 h(3) h(41) 27 h(4) h(40) 0 h(5) h(39) 65 h(6) h(38) 0 h(7) h(37) 131 h(8) h(36) 0 h(9) h(35) 239 h(10) h(34) 0 h(11) h(33) 407 h(12) h(32) 0 h(13) h(31) 665 h(14) h(30) 0 h(15) h(29) 1070 h(16) h(28) 0 h(17) h(27) 1764 h(18) h(26) 0 h(19) h(25) 3273 h(20) h(24) 0 h(21) h(23) 10358 h(22) 16384 table 24. stage 2 interpolat ion filter coefficients lower coefficient upper coefficient integer value h(1) h(19) 19 h(2) h(18) 0 h(3) h(17) 120 h(4) h(16) 0 h(5) h(15) 436 h(6) h(14) 0 h(7) h(13) 1284 h(8) h(12) 0 h(9) h(11) 5045 h(10) 8192 table 25. stage 3 interpolat ion filter coefficients lower coefficient upper coefficient integer value h(1) h(11) 7 h(2) h(10) 0 h(3) h(9) 53 h(4) h(8) 0 h(5) h(7) 302 h(6) 512 03152-prd-008 0.5 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 140 0 20 40 60 80 100 120 figure 34. 2 interpolation filter response 03152-prd-009 0.5 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 140 0 20 40 60 80 100 120 figure 35. 4 interpolation filter response 03152-prd-010 0.5 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 140 0 20 40 60 80 100 120 figure 36. 8 interpolation filter response AD9782 preliminary technical data rev. prc | page 24 of 52 AD9782 clock/data timing dll disabled, two-port data mode, dataclk as output ith the interpolation set to , the dataclk output is a delayed and inerted ersion o dacclk at the sae reuency ote that dacclk reers to the dierential cloc inputs applied at pins and as iure shows, there is a constant delay between the risin ede o dacclk and the allin ede o dataclk the dclkpol bit e it allows the data to be latched into the ad on either the risin or allin ede o dacclk ith dclkpol , the data is latched in on the risin ede o di cl, as shown in iure ith dclkpol , as shown in iure , data is latched in on the allin ede o dacclk the setup and hold ties are always with respect to the latched ede o dacclk -prd- dacclk dataclk out data t t d ns tp t ns tp t s ns tp iure data tiin, dll o, nterpolation, dclkpol -prd- dacclk dataclk out data t d ns tp t ns tp t s ns tp iure data tiin, dll o, nterpolation, dclkpol preliminary technical data AD9782 rev. prc | page 25 of 52 with the interpolation set to 2, the dacclk input runs at twice the speed of the dataclk. data is latched into the AD9782?s inputs on every other rising edge of dacclk, as shown in figure 40 and figure 41. with dclkpol = 1, as shown in figure 40, the latching edge of dacclk is the rising edge that occurs just before the falling edge of dataclk. with dclkpol = 0, as in figure 41, the latching edge of dacclk is the rising edge of dacclk that occurs just before the rising edge of dataclk. the setup and hold time values are identical to those in figure 37 and figure 38. note that there is a slight difference in the delay from the rising edge of dacclk to the falling edge of dataclk, and the delay from the rising edge of dacclk to the rising edge of dataclk. as figure 39 shows, the dataclk duty cycle is slightly less than 50%. this is true in all modes. with the interpolation set to 4 or 8, the dacclk input runs at 4 or 8 the speed of the dataclk output. the data is latched in on a rising edge of dacclk, similar to the 2 interpolation mode. however, the latching edge is every fourth edge in 4 interpolation mode and every eighth edge in the 8 interpolation mode. again, similar to operation in the 2 interpolation mode, with dclkpol = 1, the latching edge of dacclk is the rising edge that occurs just before the falling edge of dataclk. with dclkpol = 0, the latching edge of dacclk is the rising edge that occurs just before the rising edge of dataclk. the setup and hold time values are identical to those in 1 and 2 interpolation 03152-prd-068 figure 39. 03152-prd-069 dacclk in dataclk out data t d = 5ns typ t h = 2.9ns typ t s = ?0.5ns typ figure 40. data timing, dll off, 2 interpolation, dclkpol = 1 03152-prd-070 dacclk in dataclk out data t d = 6ns typ t h = 2.9ns typ t s = ?0.5ns typ figure 41. data timing, dll off, 2 interpolation, dclkpol = 0 AD9782 preliminary technical data rev. prc | page 26 of 52 dataadjust synchronization hen desinin the diital interace or hih speed dacs, care ust be taen to ensure that the dac input data eets setup- and-hold reuireents oten, copensation ust be used in the cloc delay path to the diital enine driin the dac the ad has the on chip capability to ary the dacclks latchin ede ith the interpolation unction enabled, this allows the user the choice o ultiple edes upon which to latch the data or instance, i the ad is usin interpolation, the user ay latch ro one o eiht edes beore the risin ede o dataclk, or seen edes ater this risin ede the speciic ede upon which data is latched is controlled by sp eister h, its table shows the relationship o the latchin ede o dacclk and dataclk with the arious settins o the dataadj bits table 26. spi reg 05h bit 7 bit 6 bit 5 bit 4 latching edge wrt dataclk 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 7 1 0 1 0 6 1 0 1 1 5 1 1 0 0 4 1 1 0 1 3 1 1 1 0 2 1 1 1 1 1 note that the data in figure 40 and figure 41 was taken with the dataad default of 0000. ith dclkpol = 0, the latching edge of dacclk is just preious to the rising edge of dataclk with dclkpol = 1, the latching edge of dacclk is just preious to the falling edge of dataclk. ith 8 interpolation, the user has the capability of using one of 16 edges to latch the data. this is due to the fact that there are eight dac clock edges before and after the dataclk until the next dataclk latching edge. ith 4 interpolation, there are only four latching edges of dacclk aailable before and after each dataclk edge. therefore, in 4 interpolation, only the een numbered alues for dataad are aailable, and the options are changed from 3 cycles to 4 cycles. ith 2 interpolation, there are only two edges aailable before and after dataclk, so the choices for dataad are diminished to 1 cycle to 2 cycles. figure 42, figure 43, and figure 44 show the alignment for the latching edge of dacclk with 4 interpolation and different settings for dataad. in figure 42, dataad is set to 0000, with dclkpol set to 0 so that the latching edge of dacclk is immediately before the rising edge of dataclk. the data transitions shown in figure 42 are synchronous with the dacclk, so that dacclk and data are constant with respect to each other. the only isible change when dataad is altered is that dataclk moes, indicating the latching edge has moed as well. note that when dataad is altered, the latching edge with respect to dataclk remains the same, but the latching edge of dacclk follows the edge of dataclk. 03152-prd-071 rising edge of dataclk concurrent ith latching edge of dacclk data transition dacclk latching edge figure 42. dataad = 0000 figure 43 shows the same conditions, but now dataad is set to 1111. this moes dataclk to the left in the plot, indicating that it occurs one dacclk cycle before it did in figure 42. as explained preiously, the latching edge of dacclk also moes one cycle back in time. 03152-prd-072 rising edge of dataclk concurrent ith latching edge of dacclk data transition dacclk latching edge figure 43. dataad = 1111 preliminary technical data AD9782 rev. prc | page 27 of 52 figure 44 shows the same conditions, with dataadj now set to 0001, thus moving dataclk to the right in the plot. this indicates that it occurs one dacclk cycle after it did in figure 42. now the latching edge of dacclk moves forward in time one cycle. 03152-prd-073 rising edge of dataclk concurrent with latching edge of dacclk data transition dacclk latching edge figure 44. dataadj = 0001 interpolation modes table 27. interp1 interp0 mode 0 0 no interpolation 0 1 2 interpolation 1 0 4 interpolation 1 1 8 interpolation interpolation is the process of increasing the number of points in a time domain waeform by approximating points between the input data points on a uniform time grid, this produces a higher output data rate. applied to an interpolation dac, a digital interpolation filter is used to approximate the interpo- lated points, haing an output data rate increased by the interpolation factor. interpolation filter responses are achieed by cascading indiidual digital filter banks, whose filter coefficients are gien in table 1 filter responses are shown in figure 34. the digital filters freuency domain response exhibits symmetry about half the output data rate and dc. it will cause images of the input data to be shaped by the interpolation filters freuency response. this has the adantage of causing input data images, which fall in the stop band of the digital filter to be rejected by the stop-band attenuation of the interpolation filter input data images falling in the interpolation filters pass- band will be passed. in band-limited applications, the images at the output of the dac must be limited by an analog reconstruc- tion filter. the complexity of the analog reconstruction filter is determined by the proximity of the closest image to the reuired signal band. higher interpolation rates yield larger stop-band regions, suppressing more input images and resulting in a much relaxed analog reconstruction filter. a dac shapes its output with a sinc function, haing a null at the sampling freuency of the dac. the higher the dac sam- pling rate compared to the input signal bandwidth, the less the dac sinc function will shape the output. figure 45 shows the interpolation filters of the AD9782 under different interpolation rates, normalized to the input data rate, f sin . the higher the interpolation rate the more input data images fall in the interpolation filter stop band and are rejected the band-width between passed images is larger with higher interpolation factors. the sinc function shaping is also reduced with a higher interpolation factor. table 28. mode sinc shaping at 0.43f sin (db) bandwidth to first image no interpolation 2.8241 f sin 2 interpolation 0.6708 2f sin 4 interpolation 0.1657 4f sin 8 interpolation 0.0413 8f sin AD9782 preliminary technical data rev. prc | page 28 of 52 ?8 ?6 ?4 ?2 ?0 2 4 6 8 ? 150 ? 100 ?50 0 ?8 ?6 ?4 ?2 0 2 4 6 8 ? 150 ? 100 ?50 0 ?8 ?6 ?4 ?2 0 2 4 68 ? 150 ? 100 ?50 0 ?8 ?6 ?4 ?2 0 2 4 68 ? 150 ? 100 ?50 0 no interpolation 4 interpolation 2 interpolation 8 interpolation sinc response f sin f sin f sin f sin interp[1] = 1 interp[0] = 1 interp[1] = 1 interp[0] = 0 interp[1] = 0 interp[0] = 1 interp[1] = 0 interp[0] = 0 03152-prd-011 figure 45. interpolation modes real and complex signals a complex signal contains both magnitude and phase information. given two signals at the same frequency, if a point in time can be taken such that the signal leading in phase is cosinusoidal and the lagging signal is sinusoidal, then information pertaining to the magnitude and phase of a combination of the two signals can be derived; the combination of the two signals can be considered a complex signal. the cosine and sine can be represented as a series of exponentials; recalling that a multiplication by j is a counter clockwise rotation about the re/im plane, the phasor representation of a complex signal, with frequency f, can be shown figure 46. im re c re im a/2 a/2 a/2 a/2 frequency 0 +f ?f a 2 s ft c = ae 2 s ft = acos(2 s ft) + jasin(2 s ft) acos(2 s ft) = a = [ e +j2 s ft + e ?j2 s ft ] e +j2 s ft + e ?j2 s ft 2 a 2 asin(2 s ft) = a = [ j e +j2 s ft + e ?j2 s ft ] e +j2 s ft + e ?j2 s ft 2j a 2 03152-prd-012 figure 46. complex phasor representation the cosine term represents a signal on the real plane with mirror symmetry about dc; this is referred to as the real, in- phase or i component of a complex signal. the sine term represents a signal on the imaginary plane with mirror asymmetry about dc; this term is referred to as the imaginary, quadrature or q complex signal component. the AD9782 has two channels of interpolation filters, allowing both i and q components to be shaped by the same filter transfer function. the interpolation filters? frequency response is a real transfer function. two dacs are required to represent a complex signal. a single dac can only synthesize a real signal. when a dac synthesizes a real signal, negative frequency components fold onto the positive frequency axis. if the input to the dac is mirror symmetrical about dc, the folded negative frequency components fold directly onto the positive frequency components in phase producing constructive signal summation. if the input to the dac is not mirror symmetric about dc, negative frequency components may not be in phase with positive frequency components and will cause destructive signal summation. different applications may or may not benefit from either type of signal summation. preliminary technical data AD9782 rev. prc | page 29 of 52 modulation modes table 29. single channel modulation moddual channel mod1 mod0 mode 0 0 0 0 i channel, no modulation 0 0 0 1 i channel, modulation by f dac /2 0 0 1 0 i channel, modulation by f dac /4 0 0 1 1 i channel, modulation by f dac /8 0 1 0 0 channel, no modulation 0 1 0 1 channel, modulation by f dac /2 0 1 1 0 channel, modulation by f dac /4 0 1 1 1 channel, modulation by f dac /8 either channel of the AD9782s interpolation filter channels can be routed to the dac and modulated. in single channel operation the input data may be modulated by a real sinusoid the input data and the modulating sinusoid will contain both positie and negatie freuency components. a double sideband output results when modulating two real signals. at the dac output the positie and negatie freuency components will add in phase resulting in constructie signal summation. as the modulating sinusoidal freuency becomes a larger fraction of the dac update rate, f dac, the more the sinc function of the dac shapes the modulated signal bandwidth, and the closer the first image moes. as the AD9782 interpolation filters pass band represents a large portion of the input datas nyuist band, under certain modulation and interpolation modes it is possible for modulated signal bands to touch or oerlap images if sufficient interpolation is not used. figure 48 shows the effect of real modulation under all interpolation modes. the sinc shaping at the corners of the modulated signal band and the bandwidth to the first image for those cases whose pass bands do not touch or oerlap are tabulated. table 30. interpolation modulation none 2 4 8 none f sin 2 f sin 4 f sin 8 f sin f dac /2 f sin 2 f sin 4 f sin 8 f sin f dac /4 oerlap touching 2 f sin 4 f sin f dac /8 oerlap oerlap touching 6 f sin table 31. interpolation modulation none 2 4 8 none 0 0 0 0 2.8241 0.6708 0.1657 0.0413 f dac /2 0.0701 1.1932 2.3248 3.0590 22.5378 9.1824 6.1190 4.9337 f dac /4 oerlap touching 0.2921 0.5974 1.9096 1.3607 f dac /8 oerlap oerlap touching 0.0727 0.4614 modulated pass band edges sinc shaping(lower/upper). AD9782 preliminary technical data rev. prc | page 30 of 52 0 ? f dac ?7 f dac /8 ?3 f dac /4 ?5 f dac /8 ? f dac /2 ?3 f dac /8 ? f dac /4 ? f dac/8 f dac/8 f dac/4 3 f dac/8 f dac/2 5 f dac/8 3 f dac/4 7 f dac/8 f dac filtered interpolation images f s /8 modulation ? f dac ?7 f dac /8 ?3 f dac /4 ?5 f dac /8 ? f dac /2 ?3 f dac /8 ? f dac /4 ? f dac/8 f dac/8 f dac/4 3 f dac/8 f dac/2 5 f dac/8 3 f dac/4 7 f dac/8 f dac 03152-prd-013 figure 47. double sideband modulation ?8 ?6 ?4 ?2 0 2 4 68 ? 150 ? 100 ?50 0 no interpolation 2 interpolation f sin f sin 4 interpolation f sin 8 interpolation f sin interp[1] = 0 interp[0] = 0 mod[1] = 0 mod[0] = 1 interp[1] = 0 interp[0] = 1 mod[1] = 0 mod[0] = 1 interp[1] = 1 interp[0] = 0 mod[1] = 0 mod[0] = 1 interp[1] = 1 interp[0] = 1 mod[1] = 0 mod[0] = 1 ?8?6?4?202468 ? 150 ? 100 ?50 0 ?8?6?4?202468 ? 150 ? 100 ?50 0 ?8 ?6 ?4 ?202468 ? 150 ? 100 ?50 0 03152-prd-014 figure 48. real modulation by f dac /2 under all interpolation modes preliminary technical data AD9782 rev. prc | page 31 of 52 ?8 ?6 ?4 ?2 0 2 4 68 ?150 ?100 ?50 0 no interpolation 2 interpolation f sin 4 interpolation 8 interpolation interp[1] = 0 interp[0] = 0 mod[1] = 1 mod[0] = 0 ?8 ?6 ?4 ?2 0 2 468 ?150 ?100 ?50 f sin interp[1] = 0 interp[0] = 1 mod[1] = 1 mod[0] = 0 ?8 ?6 ?4 ?2 0 2 4 6 8 ?150 ?100 AD9782 preliminary technical data rev. prc | page 32 of 52 table 32. dual channel complex modulation modsing realimag mod[1] mod[0] mode 0 0 0 0 real output, no modulation 0 0 0 1 real output, modulation by f dac /2 0 0 1 0 real output, modulation f dac /4 0 0 1 1 real output, modulation f dac /8 0 1 0 0 image output, no modulation 0 1 0 1 imag output, modulation by f dac /2 0 1 1 0 imag output, modulation by f dac /4 0 1 1 1 imag output, modulation by f dac /8 in dual channel mode, the two channels may be modulated by a complex signal, with either the real or imaginary modulation result directed to the dac. assume initially that the complex modulating signal is defined for a positive frequency only; this causes the output spectrum to be translated in frequency by the modulation factor only. no additional sidebands are created as a result of the modulation process, and therefore the bandwidth to the first image from the baseband bandwidth is the same as the output of the interpolation filters. furthermore, pass bands will not overlap or touch. the sinc shaping at the corners of the modulated signal band are tabulated. figure 52 shows the complex modulations. table 33. interpolation modulation none 2 4 8 none 0 0 0 0 C2.8241 C0.6708 C0.1657 C0.0413 f dac /2 C0.0701 C1.1932 C2.3248 C3.0590 C22.5378 C9.1824 C6.1190 C4.9337 f dac /4 C0.4680 C0.0175 C0.2921 C0.5974 C6.0630 C3.3447 C1.9096 C1.3607 f dac /8 C1.3723 C0.1160 C0.0044 C0.0727 C4.9592 C1.7195 C0.7866 C0.4614 modulated passband edges sinc shaping(lower/upper). ? f dac ?7 f dac /8 ?3 f dac /4 ?5 f dac /8 ? f dac /2 ?3 f dac /8 ? f dac /4 ? f dac /8 0 f dac /8 f dac /4 3f dac /8 f dac /2 5f dac /8 3f dac /4 7f dac /8 f dac filtered interpolation images f s /8 modulation no negative sideband ? f dac ?7 f dac /8 ?3 f dac /4 ?5 f dac /8 ? f dac /2 ?3 f dac /8 ? f dac /4 ? f dac /8 0 f dac /8 f dac /4 3f dac /8 f dac /2 5f dac /8 3f dac /4 7f dac /8 f dac 03152-prd-018 figure 51. complex modulation preliminary technical data AD9782 rev. prc | page 33 of 52 03152-prd-019 ?8 ?6 ?4 ?2 0 2 4 68 ? 150 ? 100 ?50 0 0 0 2interpolation 4interpolation 8interpolation f sin ?8 ?6 ?4 ?2 0 2 4 6 8 ? 150 ? 100 ?50 f sin ?8 ?6 ?4 ?2 0 2 4 6 8 ? 150 ? 100 ?50 f sin interp[1] = 0 interp[0] = 1 mod[1] = 0 mod[0] = 1 interp[1] = 1 interp[0] = 0 mod[1] = 0 mod[0] = 1 interp[1] = 1 interp[0] = 1 mod[1] = 0 mod[0] = 1 figure 52. complex modulation by f dac /2 under all interpolation modes ?8 ?6 ?4 ?2 0 2 4 68 ? 150 ? 100 ?50 0 2 interpolation 4 interpolation 8 interpolation f sin interp[1] = 0 interp[0] = 1 mod[1] = 1 mod[0] = 0 ?8 ?6 ?4 ?2 0 2 4 6 8 ? 150 ? 100 ?50 0 f sin interp[1] = 1 interp[0] = 0 mod[1] = 1 mod[0] = 0 ?8 ?6 ?4 ?2 0 2 4 68 ? 150 ? 100 ?50 0 f sin interp[1] = 1 interp[0] = 1 mod[1] = 1 mod[0] = 0 03152-prd-020 figure 53. complex modulation by f dac /4 under all interpolation modes ?8 ?6 ?4 ?2 0 2 4 68 ?150 ?100 ?50 0 2 interpolation 4 interpolation 8 interpolation f sin interp[1] = 0 interp[0] = 1 mod[1] = 1 mod[0] = 1 ?8 ?6 ?4 ?2 0 2 4 68 ?150 ?100 ?50 0 f sin interp[1] = 1 interp[0] = 0 mod[1] = 1 mod[0] = 1 ?8 ?6 ?4 ?2 0 2 4 68 ?150 ?100 ?50 0 f sin interp[1] = 1 interp[0] = 1 mod[1] = 1 mod[0] = 1 03152-prd-021 figure 54. complex modulation by f dac /8 under all interpolation modes AD9782 preliminary technical data rev. prc | page 34 of 52 power dissipation the AD9782 has seven power supply domains: two 3.3 v analog domains (avdd1 and avdd2), two 2.5 v analog domains (advdd and acvdd), one 2.5 v clock domain (clkvdd), and two digital domains (dvdd, which runs from 2.5 v, and drvdd, which can run from 2.5 v or 3.3 v). the current needed for the 3.3 v analog supplies, avdd1 and avdd2, is consistent across speed and varying modes of the AD9782. nominally, the current for avdd1 is 29 ma across all speeds and modes, while the current for avdd2 is 20 ma. the current for the 2.5 v analog supplies and the digital supplies varies depending on speed and mode of operation. figure 55, figure 56, and figure 57 show this variation. note that clkvdd, advdd, and acvdd vary with clock speed and interpolation rate, but not with modulation rate. 03152-prd-077 f data (msps) 250 0 25 50 75 100 125 150 175 200 225 idvdd (ma) 0 425 325 300 275 250 225 200 175 400 375 350 150 125 100 75 50 25 1 2 2 fs/4 2 fs/8 4 4 fs/4 4 fs/8 8 8 fs/4 8 fs/8 figure 55. dvdd supply current vs . clock speed, interpolation, and modulation rates 03152-prd-078 f data (msps) 250 0 25 50 75 100 125 150 175 200 225 idvdd (ma) 0 60 50 40 30 20 10 2 1 4 8 figure 56. clkvdd supply current vs. clock speed and interpolation rates 03152-prd-079 f data (msps) 250 0 25 50 75 100 125 150 175 200 225 idvdd (ma) 0 30 25 20 15 10 5 2 1 4 8 figure 57. advdd and acvdd supply current vs. clock speed and interpolation rates preliminary technical data AD9782 rev. prc | page 35 of 52 filtered interpolation images f s /8 modulation f s /4 modulation ? f dac ?7 f dac /8 ?3 f dac /4 ?5 f dac /8 ? f dac /2 ?3 f dac /8 ? f dac /8 0 0 0 f dac /8 f dac /4 3f dac /8 f dac /2 5f dac /8 3f dac /4 7f dac /8 f dac ? f dac /4 ? f dac ?7 f dac /8 ?3 f dac /4 ?5 f dac /8 ? f dac /2 ?3 f dac /8 ? f dac /8 f dac /8 f dac /4 3f dac /8 f dac /2 5f dac /8 3f dac /4 7f dac /8 f dac ? f dac /4 ? f dac ?7 f dac /8 ?3 f dac /4 ?5 f dac /8 ? f dac /2 ?3 f dac /8 ? f dac /8 f dac /8 f dac /4 3f dac /8 f dac /2 5f dac /8 3f dac /4 7f dac /8 f dac ? f dac /4 03152-prd-022 figure 58. complex modulation with negative frequency aliasing dual channel complex modulation with hilbert table 34. hilbert mode 0 hilbert transform off 1 hilbert transform on hen complex modulation is performed, the entire spectrum is translated by the modulation factor. if the resulting modulated spectrum is not mirror symmetric about dc, when the dac synthesizes the modulated signal, negatie freuency compo- nents will fall on the positie freuency axis and can cause destructie summation of the signals. for some applications, this can be seen as distorting the modulated output signal. re im f re im f re im f re im f 00 00 a/2 a/2 a/2 a/2 a a a/2 a/2 a/2 a/2 a/2 a/2 a/2 a/2 x = ae j2 s (f fm)t = ae j2 s (f fm)t s /2 = hilbert() c = x 03152-prd-023 figure 59. negatie freuency image rejection by performing a second complex modulation with a modu- lating signal haing a fixed s /2 phase difference, figure 59 (), relatie to the original complex modulation signal, figure 59 (x), taking the hilbert transform of the new resulting complex modulation, and subtracting it from the original complex mod- ulation output all negatie freuency components can be folded in phase to the positie freuency axis before being synthesized by the dac. hen the dac synthesizes the modulated output there are no negatie freuency components to fold onto the positie freuency axis out of phase conseuently no distortion is produced as a result of the modulation process. 03152-prd-024 0.5 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 dbfs 150 0 50 100 aliased negative freuenc interpolation images figure 60. negatie freuency aliasing distortion AD9782 preliminary technical data rev. prc | page 36 of 52 figure 60 shows this effect at the dac output for a mirror asymmetic signal about dc produced by complex modulation without a hilbert transform. the signal bandwidth was nar- rowed to show the aliased negative frequency interpolation images. in contrast, figure 61 shows the same waveform with the hilbert transform applied. clearly, the aliased interpolation images are not present. 03152-prd-025 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 dbfs ?150 0 ?50 ?100 figure 61. effects of hilbert transform if the output of the AD9782 is to be used with a quadrature modulator, negative frequency images are cancelled without the need of a hilbert transform. hilbert transform implementation the hilbert transform on the AD9782 is implemented as a 19- coefficient fir. the coefficients are given in table 35 table 35. coefficient integer value h(1) 6 h(2) 0 h(3) 17 h(4) 0 h(5) 40 h(6) 0 h(7) 91 h(8) 0 h(9) 318 h(10) 0 h(11) 318 h(12) 0 h(13) 91 h(14) 0 h(15) 40 h(16) 0 h(17) 17 h(18) 0 h(19) 6 the transfer function of an ideal hilbert transform has a 90 phase shift for negatie freuencies, and a 90 phase shift for positie freuencies. because of the discontinuities that occur at 0 hz and at 0.5 sample rate, any real implementation of the hilbert transform trades off bandwidth ersus ripple. figure 62 and figure 63 show the gain of the hilbert transform ersus freuency. gain is essentially flat, with a pass-band ripple of 0.1db oer the freuency range 0.07 sample rate to 0.43 sample rate. figure 64 shows the phase response of the hilbert transform implemented in the AD9782. the phase response for positie freuencies begins at 90 at 0 hz, followed by a linear phase response (pure time delay) eual to nine filter taps (nine clock cycles). for negatie freuencies, the phase response at 0 hz is 90, again followed by a linear phase delay of nine filter taps. to compensate for the unwanted 9-cycle delay, an eual delay of nine taps is used in the AD9782 digital signal path opposite to the hilbert transform. this delay block is noted as t on the data sheet. 03152-prd-074 1000 100 200 300 400 500 600 700 800 900 100 10 20 60 0 40 30 70 80 90 10 50 figure 62. hilbert transform gain 03152-prd-075 1000 100 200 300 400 500 600 700 800 900 1.0 1.0 0.4 0.4 0.8 0 0.2 0.6 0.8 0.6 0.2 figure 63. hilbert transform ripple preliminary technical data AD9782 rev. prc | page 37 of 52 03152-prd-076 1200 100 200 400 600 800 1000 ?4 4 3 ?1 1 2 ?2 ?3 0 figure 64. phase response of hilbert transform table 36. dual channel complex modulation sideband selection sideband mode 0 lower if sideband rejected 1 upper if sideband rejected 0 90 AD9782 AD9782 lo i im() re() 03150-prd-003 figure 65. AD9782 driing uadrature modulator the AD9782 can be configured to drie a uadrature modula- tor, representatiely as in figure 65. here two AD9782s are used with one AD9782 producing the real output, the second AD9782 produces the imaginary output. by configuring the AD9782 as a complex modulator coupled to a uadrature modulator, if image rejection is possible. the uadrature modulator acts as the real part of a complex modulation pro- ducing a double sideband spectrum at the local oscillator (lo) freuency, with mirror symmetry about dc. a baseband double sideband signal modulated to if increases if filter complexity and reduces power efficiency. if the base- band signal is complex, a single sideband if modulation can be used, relaxing if filter complexity and increasing power efficiency. the AD9782 has the ability to place the baseband single side- band complex signal either aboe the if freuency or below it. figure 66 illustrates the baseband selection. 03152-prd-027 0.5 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 dbfs 150 0 50 100 figure 66. upper if sideband rejected 03152-prd-028 0.5 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 dbfs 150 0 50 100 figure 67. lower if sideband rejected AD9782 preliminary technical data rev. prc | page 38 of 52 0 0 f if ?f if ? f if f if 0 ? f if f if baseband if sideband = 0 sideband = 1 03152-prd-029 figure 68. if quadrature modulation of real and complex baseband signals table 37. data port synchronization plockext dclkext modsnc dclkcrc mode function 1 x x x pll output pll locked flag output, synchronizer disabled 0 0 0 x dataclk master cha nnel data rate clock output 0 0 1 x modulator master modula tor synchronization clock output 0 1 0 0 dataclk slae input cha nnel data rate clock, dll off 0 1 0 1 dataclk slae input cha nnel data rate clock, dll on 0 1 1 0 modulator slae input modula tor synchronizer clock, dll off 0 1 1 1 modulator slae input modula tor synchronizer clock, dll on in applications where two or more AD9782s are used to synthe- size seeral digital data paths, it may be necessary to ensure that the digital inputs to each deice are latched synchronously. in complex data processing applications, digital modulator phase alignment may be reuired between two AD9782s. in order to allow data synchronization and phase alignment, only one AD9782 should be configured as a master deice, proiding a reference clock for another slae-configured AD9782. ith synchronization enabled, a reference clock signal is generated on the dataclk/plllock pin of the master. the dataclk/plllock pins on the slae deices act as inputs for the reference clock generated by the master. the dataclk/ plllock pin on the master and all slaes must be directly connected. all master and slae deices must hae the same clock source connected to their respectie clk/clk pins. hen configured as a master, the reference clock generated may take one of two forms. in modulator master mode, the reference clock will be a suare wae with a period eual to 16 cycles of the dac update clock. internal to the AD9782 is a 16-state finite state machine, running at the dac update rate. this state machine generates all internal and external synchronization clocks and modulator phasings. the rising edge of the master reference clock is time aligned to the internal state machines state zero. slae deices use the masters reference clock to synchronize their data latching and align their modulators phase by aligning their local state machine state zero to the master. the second master mode, dataclk master mode, generates a reference clock that is at the channel data rate. in this mode, the slae deices align their internal channel data rate clock to the master. if modulator phase alignment is needed, a concurrent serial write to all slae deices is necessary. to achiee this, the csb pin on all slaes must be connected together and a group serial write to the modad register bits must be performed the modulator coefficient alignment is updated on the next rising edge of the internal state machine following a successful serial write, figure 69. modulator master mode does not need a concurrent serial write as slaes lock to the master phase automatically. in a slae deice, the local channel data rate clock and the digital modulator clock are created from the internal state machine. the local channel data rate clock is used by the slae to latch digital input data. at high data rates, the delay inherent in the signal path from master to slae may cause the slae to lag the master when acuiring synchronization. to account for this, an integer number of the dac update clock cycles may be programmed into the slae deice as an offset. the alue in datad allows the local channel data rate clock in the slae deice to adance by up to eight cycles of the dac clock or delayed by up to seen cycles, figure 70. the digital modulator coefficients are updated at the dac clock rate and decoded in seuential order from the state machine according to figure 71. the modad bits can be used to align a different coefficient to the finite state machines zero state as shown in figure 72. preliminary technical data AD9782 rev. prc | page 39 of 52 dac clock state machine state machine channel data cycle clock rate clock modulator coefficient modadj 000 000 10?1010?1010?1010?10?1010?1010?1010?1010 01234567891011121314150123456789101112131415 03152-prd-030 figure 69. synchronous serial modulator phase alignment datadj[3:0] dac clock received channel data rate clock local channel data rate clock 0000 0001 1111 03152-prd-031 ?1 +1 figure 70. local channel data rate clock synchronized with offset 1 fs/2 state 2 3 4 5 6 7 8 9 10 11 12 13 4 15 1 0 0 1 03152-prd-032 decode 0 0 0 0 0 ?1 0 0 0 0 0 1 1/ 2 ?1/ 2 ?1/ 2 ?1/ 2 fs/4 1 2 3 0 fs/8 1234567 0 figure 71. digital modulator state machine decode modadj[2:0] dac clock state machine cycle clock 000 101 010 state machine modulator coefficient 03152-prd-033 ?1 0 1 0 ?1 0 0 ?1 0 1 0 ?1 0 14150123 1501 15012 figure 72. local modulator coefficient synchronized with offset AD9782 preliminary technical data rev. prc | page 40 of 52 operating the AD9782 rev e evaluation board this section helps the user get started with the AD9782 evaluation board. because it is intended to provide starter information to power up the board and verify correct operation, a description of some of the more advanced modes of operation has been omitted. for a description of the various spi registers and the effect they have on the operating modes of the AD9782, see the mode control (via spi port) section. power supplies the AD9782 rev e evaluation board has five power supply connectors, labeled vddin, cvdin, vdd2in, vdd3in, and avdin. the AD9782 itself actually has seven power supply domains. to reconcile the power supply domains on the chip with the power supply connectors on the evaluation board, use table 38. additionally, the drvdd power supply on the AD9782 is used to supply power for the digital input bus. drvdd can be run from 2.5 v or 3.3 v. on the evaluation board, drvdd is jumper selectable by jp1, just to the left of the chip on the evaluation board. with the jumper set to the 3.3 v position, drvdd chip receives its power from vdd3in. with the jumper set to the 2.5 v position, drvdd receives its power from avdin. pecl clock driver the AD9782 system clock is driven from an external source via connector s1. the AD9782 evaluation board includes an onsemiconductor mc100ept22 pecl clock driver. in the factory, the evaluation board is set to use this pecl driver as a single-ended-to-differential clock receiver. the pecl driver can be set to run from 2.5 v from the cvdin power connector, or 3.3 v from the vdd3in power connector. this setting is done via jumper, jp2, situated next to the cvdin power connector, and by setting input bias resistors r23 and r4 on the evaluation board. the factory default is for the pecl driver to be powered from cvdin at 2.5 v (r23 = 90.9 ?, r4 = 115 ?). to operate the pecl driver with a 3.3 v supply, r23 must be replaced with a 115 ? resistor and r4 must be replaced with a 115 ? resistor, as well as changing the position of jp2. the schematic of the pecl driver section of the evaluation board is shown below in figure 73. a low jitter sine wave can be used as the clock source. care must be taken to make sure the clock amplitude does not exceed the power supply rails for the pecl driver. 03152-prd-080 u2 7 1 2 cond;5 clkvdds;8 c32 0.1 f r23 115 ? r4 90.9 ? a clk x clkvdds r5 50 ? r7 50 ? r6 50 ? clkvdds mc100ept22 clk+ clk? figure 73. pecl driver on AD9782 rev e evaluation board table 38. evaluation board label ps domain on chip nominal power supply voltage (v) description vddin dvdd 2.5 spi port cvdin clkvdd 2.5 clock circuitry vdd2in acvdd and advdd 2.5 analog circuitry co ntaining clock and digital interface circuitry vdd3in avdd2 3.3 switching analog circuitry avdin avdd1 3.3 analog output circuitry preliminary technical data AD9782 rev. prc | page 41 of 52 data inputs digital data inputs to the AD9782 are accessed on the evaluation board through connectors j1 and j2. these are 40 pin right angle connectors that are intended to be used with standard ribbon cable connectors. the input levels should be either 3.3 v or 2.5 v cmos, depending on the setting of the drvdd jumper jp1. the data format is selectable through register 02h, bit 7 (datafmt). with this bit set to a default 0, the AD9782 assumes that the input data is in twos complement format. with this bit set to 1, data should be input in offset binary format. when the evaluation board is first powered up and the clock and data are running, it is recommended that the proper operating current is verified. depress reset switch sw1 to ensure that the AD9782 is in the default mode. the default mode for the AD9782 is for the internal pll to be disabled, and the interpolation set to 1. the modulator is turned off in the default mode. the nominal operating currents for the evaluation board in the power-up default mode are shown in table 39. additionally, the drvdd power supply on the AD9782 is used to supply power for the digital input bus. drvdd can be run from 2.5 v or 3.3 v. on the evaluation board, drvdd is jumper selectable by jp1, just to the left of the chip on the evaluation board. with the jumper set to the 3.3 v position, drvdd chip receives its power from vdd3in. with the jumper set to the 2.5 v position, drvdd receives its power from avdin. spi port sw1 is a hard reset switch that sets the AD9782 to its default state. it should be used every time the AD9782 power supply is cycled or the clock is interrupted, or if new data is to be written via the spi port. for a description of the various spi registers and the effect they have on the operating modes of the AD9782, see the mode control (via spi port) section. set the spi software to read back data from the AD9782 and verify that when the software is run, the expected values are read back. operating with pll disabled the spi registers referenced in this section are shown in table 40. with the pll disabled, the evaluation board clock input must be run at the intended dac sample rate, up to the specified limit of 500 msps. at the same time, the interpolation rate should be set so the input data rate does not exceed the 200 msps limit. in the default mode with the pll disabled, the dataclk signal from the AD9782 is available at connector s2. the rate of this clock is the system clock applied at s1, divided by the interpolation rate. dataclk can be used to synchronize the external data into the AD9782. table 39. nominal operating curre nts in power-up default mode nominal current @ speed (ma) evaluation board power supply 50 msps 100 msps 150 msps 200 msps vddin 24 49 74 99 cvdin 79 83 87 92 vdd2in 1 4 6 8 vdd3in 30 30 30 30 avdin 27 27 27 27 table 40. spi registers register bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 01h interp[1] interp[0] 04h pllon pllmult[1] pllmult[0] plldiv[1] plldiv[0] plockext interpolation rate pll multiplier pll divider bit 7 bit 6 rate bit 6 bit 5 mult bit 4 bit 3 div 0 0 1 0 0 2 0 0 1 0 1 2 0 1 4 0 1 2 1 0 4 1 0 8 1 0 4 1 1 8 1 1 16 1 1 8 AD9782 preliminary technical data rev. prc | page 42 of 52 operating with pll enabled note that a specific revision of the AD9782 on the rev e evaluation board has a nonfunctioning pll. this revision can be identified by the xxx. with the AD9782 pll enabled, the evaluation board clock input must be run at the data input rate, up to the specified 200 msps limit. the pll controls the internal clock multiplication and drives the interpolation filters and digital modulator. the internal pll has a vco in the control loop that is designed to operate optimally over the 200 mhz to 500 mhz range. the vco speed can be calculated as follows: vco speed input data rate pllmult [, te interpolation rate is set bits 6 and 7 it te pll enaled, te settings for te interpolation rate, te pll ultiplier, and te pll diide are interrelated te interpolation rate ust eet te folloing riteria interpolation rate [settings of bits 6, 7 [ pllmult plldivider terefore, assuing te input data rate is onstant and te vco is at optial speed, if te interpolation rate is inreased a fator of m, te pllmult setting ust e dereased te sae fator m it te pll enaled, dtcl onnetor s indiates te lo state of te pll logi fro s indiates lo a logi indiates te pll is not urrentl loed lo output te analog output of te d7 is aessed ia onnetor s one all settings are seleted and urrent leels, pll lo state, and spi port funtionalit are erified, te analog signal at s an e ieed or ost of te d7s appliations, a spetru analer is te instruent of oie to erif proper perforane tpial spetral plot is son in igure 7, it te d7 sntesiing a totone signal in te default ode it a msps saple rate single tone c signal sould proide output poer of approiatel db to te spetru analer if te spetru does not loo orret at tis point, te data input a e iolating setup and old ties it respet to te input lo to orret tis, te user sould ar te input data tiing if tis is not possile, spi register , bit an e inerted tis it ontrols te lo edge upon i te data is lated if tese etods do not orret te spetru, it is unliel tat te issue is tiing related tis note sould ten e reread to erif tat all instrutions ae een folloed prd 6 6 7 strt stop m m igure 7 tpial spetral plot preliminary technical data AD9782 rev. prc | page 43 of 52 s11 cgnd;3,4,5 s9 agnd2; 3,4,5 s7 agnd2; 3,4,5 s5 dgnd; 3,4,5 2 1 r7 50 : r5 50 : r6 50 : jp8 jp6 avdd_in advdd2_in dvdd_in tp18 blk tp30 tp31 tp32 tp33 tp34 blk blk blk blk blk blk blk tp36 c28 4.7 p f 6.3v c75 0.1 p f jp33 2 1 cgnd; 5 clkvdds; 8 2 1 7 clkvdds c35 0.1 p f jp30 c47 0.1 p f advdd acvdd c76 0.1 p f c46 22 p f 16v c45 22 p f 16v c64 22 p f 16v c68 0.1 p f c63 22 p f 16v clkvdds; 8 cgnd; 5 l9 ferrite tp13 red l8 ferrite l11 ferrite l12 ferrite tp1 red tp12 blk tp2 red tp3 blk l1 ferrite tp6 red tp5 blk c69 0.1 p f tp16 blk c48 0.1 p f avd3 l2 ferrite tp4 red avd1 avdd l3 ferrite c65 22 p f 16v aclkx l6 ferrite clkvdds c34 0.1 p f clkvdds jp10 cvd clkvdd jp5 jp36 tp7 blk advdd3_in c67 0.1 p f c29 22 p f 16v r23 115 : tp35 jp34 dvdd vdd avd2 jp9 avdd2 l13 val l10 val l7 val l14 val jp7 clkvdd_in tp17 blk clk+ clk? dvdds dvdd avdd2 drvdd smaedge smaedge smaedge smaedge smaedge agnd; 3,4,5 mc100ept22 s10 + + + + + jp1 ab 3 2 1 jp1 a b 3 r4 90.9 : c32 0.1 p f u2 + 4 3 6 mc100ept22 u2 aux clock power input filters 2.5vq 3.3vq 3.3v 2.5vn 2.5v 03152-prd-082 figure 75. power supply distribution AD9782 preliminary technical data rev. prc | page 44 of 52 03152-prd-083 spcsb bd04 spclk spsdi spsdo c6 10 p f 6.3v c22 0.001 p f c37 0.1 p f bd08 bd07 dvdd bd06 bd05 bd03 bd02 bd01 bd00 reset tp11 wht tp10 wht clk+ clk? clkcom1 clkcom2 clkvdd1 clkvdd2 dclk-plll dcom1 dcom2 dcom3 dcom4 drvdd1 dvdd1 dvdd2 dvdd3 dvdd4 lpf p1b0lsb p1b1 p1b10 p1b11 p1b12 p1b13 p1b14 p1b15msb p1b2 p1b3 p1b4 p1b5 p1b6 p1b7 p1b8 p1b9 p2b10 p2b11 p2b12 p2b13 p2b14-opclk p2b15msb-iqsel p2b9 accom2p2 accomp1 acom1p11 acom2p12 acom1p21 acom2p1 acom2p2 acvddp1 acvddp2 adcomp2 advddp1 advddp2 avdd1p1 avdd1p2 avdd2p1 avdd2p2 dcom5 dcom6 dnc1 dvdd5 dvdd6 fsadj iouta ioutb p2b0lsb p2b1 p2b2 p2b3 p2b4 p2b5 p2b6 p2b7 p2b8 refio reset sp-clk sp-sdi sp-sdo spi_csb dnc2 u1 ad9786btsp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 tp8 wht + c5 10 p f 6.3v c21 0.001 p f c38 0.1 p f dvdd + sw1 4 3 reset 2 1 drvdd float; 5 c55 0.001 p f c20 0.001 p f c49 0.1 p f avdd c18 0.001 p f c4 0.1 p f avdd2 c62 0.1 p f c61 0.001 p f c16 0.1 p f c30 10v 10 p f + r8 2.000k : 0.01% c19 0.1 p f c14 0.1 p f c2 10 p f 6.3v c17 0.1 p f c15 0.1 p f c3 10 p f 6.3v + + c66 10 p f 6.3v + acvdd adtl1-12 p s 46 31 advdd r10 49.9 : r9 49.9 : t3 p s 1 4 6 2 3 nc = 5 p s 6 3 1 5 4 nc = 5 t2a t2b tc1-1t ttwb-1-b r42 49.9 : out1 s3 s3 tp29 blk c12 0.1 p f c1 10 p f 6.3v c11 0.1 p f c42 0.1 p f c49 1pf + c26 0.001 p f c10 10 p f 6.3v c40 0.1 p f + bd09 bd10 bd11 bd12 bd13 ad00 ad01 ad02 ad03 ad04 ad05 ad06 ad07 ad08 ad09 ad10 ad11 ad12 ad13 ad14 ad15 dvdd c25 0.001 p f c9 10 p f 6.3v c41 0.1 p f + dvdd clkvdd clkvdd clk? clk+ r1 50 : 4 1 2 3 5 6 t2a t1 t1-1t s1 cgnd; 3,4,5 aclkx tp15 wht r2 10k : c13 0.1 p f r3 10k : c54 0.001 p f c33 0.1 p f c31 10 p f 6.3v + drvdd c24 0.001 p f c8 10 p f 6.3v c39 0.1 p f + dvdd c23 0.001 p f c7 10 p f 6.3v c36 0.1 p f + dvdd tp14 wht s2 s4 s6 bd15 opclk_3 iq dataclk opclk opclk bd14 jp27 jp28 a b jp23 jp22 3 2 1 dgnd; 3,4,5 dgnd; 3,4,5 agnd; 3,4,5 agnd; 3,4,5 figure 76. local circuitry preliminary technical data AD9782 rev. prc | page 45 of 52 03152-prd-084 r43 100 : r44 100 : r41 100 : r46 100 : r39 100 : r38 100 : r40 100 : r34 100 : r31 100 : r30 100 : r32 100 : r33 100 : r27 100 : r26 100 : r28 100 : r29 100 : 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 data-a ribbon j1 ax07 ax06 ax05 ax04 ax15 ax14 ax13 ax12 ax00 ax01 ax02 ax03 ax08 ax09 ax10 ax11 jp21 jp19 2 1 345678910 r1 r2 r3 r4 r5 r6 r7 r8 r9 2 1 345678910 r1 r2 r3 r4 r5 r6 r7 r8 r9 rcom rcom rp8 dnp rp6 dnp 2 1 345678910 2 1 345678910 r1 r2 r3 r4 r5 r6 r7 r8 r9 r1 r2 r3 r4 r5 r6 r7 r8 r9 rcom rcom rp7 dnp rp5 dnp ad15 ad14 ad13 ad12 ad11 ad10 ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad00 ax15 ax14 ax13 ax12 ax11 ax10 ax09 ax08 ax07 ax06 ax05 ax04 ax03 ax02 ax01 ax00 116 215 314 413 512 611 710 89 116 215 314 413 512 611 710 89 rp1 22 rp1 22 rp1 22 rp1 22 rp1 22 rp1 22 rp1 22 rp1 22 rp2 22 rp2 22 rp2 22 rp2 22 rp2 22 rp2 22 rp2 22 rp2 22 jp3 jp12 figure 77. digital data port a input terminations AD9782 preliminary technical data rev. prc | page 46 of 52 03152-prd-085 r49 100 : r51 100 : r47 100 : r52 100 : r54 100 : r55 100 : r53 100 : r56 100 : r58 100 : r57 100 : r59 100 : r63 100 : r61 100 : r62 100 : r60 100 : r64 100 : 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 data-b ribbon j2 bx07 bx06 bx05 bx04 bx15 bx14 bx13 bx12 bx00 bx01 bx02 bx03 bx08 bx09 bx10 bx11 jp25 jp24 2 1 345678910 r1 r2 r3 r4 r5 r6 r7 r8 r9 2 1 345678910 r1 r2 r3 r4 r5 r6 r7 r8 r9 rcom rcom rp10 dnp rp11 dnp 2 1 345678910 2 1 345678910 r1 r2 r3 r4 r5 r6 r7 r8 r9 r1 r2 r3 r4 r5 r6 r7 r8 r9 rcom rcom rp9 dnp rp12 dnp bd15 bd14 bd13 bd12 bd11 bd10 bd09 bd08 bd07 bd06 bd05 bd04 bd03 bd02 bd01 bd00 bx15 bx14 bx13 bx12 bx11 bx10 bx09 bx08 bx07 bx06 bx05 bx04 bx03 bx02 bx01 bx00 sdo clk sdi csb 116 215 314 413 512 611 710 89 116 215 314 413 512 611 710 89 rp3 22 rp3 22 rp3 22 rp3 22 rp3 22 rp3 22 rp3 22 rp3 22 rp4 22 rp4 22 rp4 22 rp4 22 rp4 22 rp4 22 rp4 22 rp4 22 jp26 jp31 figure 78. digital data port b input terminations preliminary technical data AD9782 rev. prc | page 47 of 52 03152-prd-086 dvdds opclk dgnd;8 dvdds;16 1 2 3 6 5 15 4 c53 0.1 p f c52 4.7 p f 6.3v c44 4.7 p f 6.3v c51 0.1 p f c43 4.7 p f 6.3v c50 0.1 p f r50 9k : r48 9k : r45 9k : opclk_3 spcsb spclk r20 10k : spsdi r21 10k : spsdo u5 12 13 11 9 10 dvdds 8 3 5 4 2 1 6 sw5 2 1 3 sdo sdi clk csb pre clr q q_ j k clk 74lcx112 u7 74ac14 74ac14 74ac14 a b spi port p1 sw4 2 1 3 a b sw3 2 1 3 a b sw2 2 1 3 a b u5 u5 u5 21 3 5 4 6 74ac14 74ac14 74ac14 u5 u5 ++ u6 13 12 10 8 11 9 74ac14 74ac14 74ac14 u6 u6 u6 12 4 6 3 5 74ac14 74ac14 74ac14 u6 u6 dgnd;8 dvdds;16 13 12 11 7 9 14 10 pre clr q q_ j k clk 74lcx112 u7 + figure 79. spi and one-port clock circuitry AD9782 preliminary technical data rev. prc | page 48 of 52 03152-prd-087 figure 80. pcb assembly, primary side 03152-prd-088 figure 81. pcb assembly, secondary side preliminary technical data AD9782 rev. prc | page 49 of 52 03152-prd-089 figure 82. pcb assembly, layer 1 metal 03152-prd-090 figure 83. pcb assembly, layer 6 metal AD9782 preliminary technical data rev. prc | page 50 of 52 03152-prd-091 figure 84. pcb assembly, layer 2 metal (ground plane) 03152-prd-092 figure 85. pcb assembly, layer 3 metal (power plane) preliminary technical data AD9782 rev. prc | page 51 of 52 03152-prd-093 figure 86. pcb assembly, layer 4 metal (power plane) 03152-prd-094 figure 87. pcb assembly, layer 5 metal (ground plane) AD9782 preliminary technical data rev. prc | page 52 of 52 outline dimensions |
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